Integrated circuits used in communication devices, such as wireless communication devices, are often required to perform signal processing in environments that are very sensitive to the introduction of a signal offset, such as noise. The signal offset represents a deviation in the intended value of a circuit reference signal introduced in the processes of transmitting and receiving signals. The signal offset may affect the DC performance of a circuit by causing a presence of an offset current or offset voltage that is indistinguishable from the reference signal, which may further lead to undesired effects, such as circuit saturation and, potentially, circuit malfunction. For example, in highly integrated wireless transceivers, DC offset may be introduced in radio frequency (RF) front end circuitries or in baseband circuitries. Such DC offset may be amplified by various amplifiers in the baseband circuitries and may cause saturation and/or undesired interference in the baseband circuitries.
Techniques have been developed to reduce or cancel DC offset by using alternating current (AC) coupled or single pole low-pass filters. For example, U.S. Pat. No. 6,509,777 issued to Razavi et al. on Jan. 21, 2003, discloses a DC offset reduction circuit using a AC coupled feedback loop with a programmable gain transconductance amplifier of programmable gain. However, such conventional techniques often require a large RC time constant, which may result in a large die footprint or size for the DC offset reduction circuit and an increase in DC offset reduction time. Under certain circumstances, the increased time for reducing or canceling the DC offset may be undesirable in many wireless communication systems, such as wireless local area network (WLAN) or world interoperability for microwave access (WiMAX), etc.
Methods and systems consistent with certain features of the disclosed embodiments are directed to solving one or more of the problems set forth above.